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www.expresscomputeronline.com WEEKLY INSIGHT FOR TECHNOLOGY PROFESSIONALS
18 April 2005  
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Home - Market - Article

30 minute interview

“We are writing history here; this is an inflection point”

David W Yen, PhD Executive Vice-president Scalable systems
Sun Microsystems

There has been considerable interest in what Sun is doing ever since you scrapped US-IV and announced Niagara and Rock. What’s the latest on that front?

Niagara is a processor that will be deployed in both boxes and blades. It will be targeted at commercial set-ups and telcos. The processor will have 8 cores that will run 4 threads each to offer 32 threads in all. The Rock processor design will offer the best of both worlds. Additional innovations around throughput and processor core architecture, as well as Java processing, will be there in the Rock chip, while single-thread performance remains very competitive. It will be out by 2007-08. We are writing history here. From a technical perspective, this is an inflection point.

In the Rock design, transistors are devoted to processing. It is meant for raw computing with a Niagara derivative as a companion chip to handle other tasks. In the case of Niagara, the design supports computing and networking interfaces. Down the line, we plan to support cryptology in Niagara with public keys stored in the chip.

There was time when MHz (later GHz) was the only measure of processor performance. That’s changed even on the desktop. What lies beyond raw gigahertz?

Speed or MHz is only one parameter through which you can measure processor performance. In real business environments, more GHz offers diminishing returns. What is important is how you ensure that the processor is 100 percent productive. Take the Alpha processor which sits idle 70 percent of the time and it’s clear that you have to feed the hungry processor.

All systems will have to employ memory interleaving. From the processor to the memory, everybody uses the same DRAM. Special attention must be given to ensure that new sub-systems match the processor step for step. My engineers are working with the Solaris and JVM/JES (Java Virtual Machine/Java Enterprise System) guys. When you start working on multi-core, multi-threaded systems, the question that comes up is—how many threads? This decision has to be related to memory latency. Then you have to figure out which market you are aiming at—data centres or Web services?

Many years ago Sun had a chip called MAJC. Has this project influenced the company’s current processor designs?

The current architect for Rock was the architect for MAJC. That chip started us thinking about multi-core, multi-threaded architecture. Some ideas from there are being applied to Rock.

While coding application software, performance improvements are obtainable by writing directly to the OS. Is something similar possible by writing directly to the hardware?

We have to be careful as Solaris-SPARC and Solaris-x86 share the same source tree. In process implementation, we try to match the integration of our application software with Solaris, and for network intensive operations we can provide a hardware assist. For the TCP/IP stack in Solaris on Niagara we will have extra hardware. Instead of doing an operation in the software, we will do it in the hardware. [Parts of] Solaris will run in Niagara [processor’s microcode].

To run Java well, you need a good implementation of threads. We have figured out a special recipe for Rock; it will run Java faster with more parallel garbage collection. We will work to resolve the locking mechanism that usually becomes a performance bottleneck.

eBay is a major customer for Sun. Does the experience of handling that kind of workload help you design processors that satisfy the requirements of your other customers?

The eBay auction workload is what I will call a ‘dotcom’ workload. A ‘business’ workload shares many of the characteristics of a ‘dotcom’ workload. In both cases, the compute demand for each thread is relatively light, but the volumes are huge. Every user who logs in creates a thread.

There are multiple instances, hundreds of thousands of them—the Niagara family of processors is optimised for that kind of workload. Rock is for the HPC (high performance computing) workload with lots of floating point operations. It will be a more traditional processor design when compared to Niagara, which will be closer to a system-on-a-chip.

You have a large development centre in India. Is any hardware work being done here?

10 percent of Sun India Engineering Centre’s 700 engineers are in my group. They are working on chip design, CAD and quality assurance work for new products. We have some people working on mainframe migration software. India and China are large territories both in terms of market and talent pool.

TI is your fab partner. How do you characterise the relationship?

TI has been a good partner. Our relationship goes beyond financial transactions. They are fabricating the UltraSPARC IV and IIIi. They are going to be the foundry for Niagara and Rock.

Throughput computing
In 2005 or 2006, Sun plans to release processors that provide 15x throughput of existing ones. After that, it wants to release systems with 30 times today’s performance. The goal is simple, if audacious—a single blade shelf that does the work of 32 of today’s 4-way servers; eight rack units instead of 160; less than 3 kilowatts of power versus 38; one blade system to manage instead of 32 servers.

Moore’s Law is slowing. CPU clock frequency that doubled every two years may double in ever-longer increments of time. Memory speeds are doubling every six years, creating a gap in the performance of chips and memory. The end-result is that today’s processors are sitting idle as often as 75 percent of the time, waiting to fetch data from the system memory.

Sun’s approach to solve this knotty problem is to use the additional transistors afforded by Moore’s Law to put multiple cores on a single piece of silicon, with each core processing multiple threads simultaneously. When one thread is waiting for memory, the affected core will start processing another thread, thereby side-stepping the memory latency issue. This approach is expected to improve chip efficiency and thereby boost application performance. Will it work? We’ll have to wait and see, but if it does, Sun would have pulled a rabbit out of its R&D hat. The company succeeded in doing that before, and there’s no telling if it might do it again.

—Prashant L Rao

 


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